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1.35v ddr3l sdram addendum mt41k256m4 C 32 meg x 4 x 8 banks mt41k128m8 C 16 meg x 8 x 8 banks mt41k64m16 C 8 meg x 16 x 8 banks description ddr3l sdram (1.35v) is a low voltage version of the ddr3 sdram (1.5v). unless stated otherwise, ddr3l sdram meets the functional and timing specifica- tions listed in the equivalent density ddr3 sdram data sheet located on www.micron.com. features ? v dd = v ddq = +1.35v (1.283v to 1.45v) ? backward compatible to v dd = v ddq = 1.5v 0.075v ? differential bidirectional data strobe ? 8 n -bit prefetch architecture ? differential clock inputs (ck, ck#) ? 8 internal banks ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? programmable cas (read) latency (cl) ? programmable cas additive latency (al) ? programmable cas (write) latency (cwl) ? fixed burst length (bl) of 8 and burst chop (bc) of 4 (via the mode register set [mrs]) ? selectable bc4 or bl8 on-the-fly (otf) ? self refresh mode ? t c of 0c to 95c C 64ms, 8192-cycle refresh at 0c to 85c C 32ms at 85c to 95c ? self refresh temperature (srt) ? automatic self refresh (asr) ? write leveling ? multipurpose register ? output driver calibration options 1 marking ? configuration C 256 meg x 4 256m4 C 128 meg x 8 128m8 C 64 meg x 16 64m16 ? fbga package (pb-free) C x4, x8 C 78-ball fbga (8mm x 11.5mm) rev. f, g jp ? fbga package (pb-free) C x16 C 96-ball fbga (8mm x 14mm) rev. g jt ? timing C cycle time C 1.25ns @ cl = 11 (ddr3-1600) -125 C 1.5ns @ cl = 9 (ddr3-1333) -15e ? revision :f, :g note: 1. not all options listed can be combined to define an offered product. use the part catalog search on http://www.micron.com for available offerings. table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl (ns) t rcd (ns) t rp (ns) cl (ns) -125 1 1600 11-11-11 13.75 13.75 13.75 -15e 1 1333 9-9-9 13.5 13.5 13.5 -187e 1066 7-7-7 13.1 13.1 13.1 note: 1. backward compatible to 1066, cl = 7 (-187e). table 2: addressing parameter 256 meg x 4 128 meg x 8 64 meg x 16 configuration 32 meg x 4 x 8 banks 16 meg x 8 x 8 banks 4 meg x 16 x 8 banks refresh count 8k 8k 8k row address 16k a[13:0] 16k a[13:0] 8k a[12:0] 1gb: x4, x8, x16 ddr3l sdram addendum description pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing (continued) parameter 256 meg x 4 128 meg x 8 64 meg x 16 bank address 8 ba[2:0] 8 ba[2:0] 8 ba[2:0] column address 2k a[11, 9:0] 1k a[9:0] 1k a[9:0] page size 1kb 1kb 2kb 1gb: x4, x8, x16 ddr3l sdram addendum description pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
ball assignments and descriptions figure 1: 78-ball fbga C x4, x8 ball assignments (top view) 1 2 3 4 6 7 8 9 5 v ss v ss v ddq v ssq v refdq nc odt nc v ss v dd v ss v dd v ss v dd v ssq dq2 n f , dq6 v ddq v ss v dd cs# ba0 a3 a5 a7 reset# nc dq0 dqs dqs# nf, dq4 ras# cas# we# ba2 a0 a2 a9 a13 n f , nf/tdqs# dm, dm/tdqs dq1 v dd n f , dq7 ck ck# a10/ap nc a12/bc# a1 a11 nc v dd v ddq v ssq v ssq v ddq nc cke nc v ss v dd v ss v dd v ss v ss v ssq dq3 v ss n f , dq5 v ss v dd zq v refca ba1 a4 a6 a8 a b c d e f g h j k l m n notes: 1. ball descriptions listed in table 3 (page 5) are listed as x4, x8 if unique; otherwise, x4 and x8 are the same. 2. a comma separates the configuration; a slash defines a selectable function. example: d7 = nf, nf/tdqs#. nf applies to the x4 configuration only. nf/tdqs# applies to the x8 configuration onlyselectable between nf or tdqs# via mrs (symbols are de- fined in table 3). 1gb: x4, x8, x16 ddr3l sdram addendum ball assignments and descriptions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
figure 2: 96-ball fbga C x16 ball assignments (top view) 1 2 3 4 6 7 8 9 5 a b c d e f g h j k l m n p r t v ddq v ssq v ddq v ssq v ss v ddq v ssq v refdq nc odt nc v ss v dd v ss v dd v ss dq13 v dd dq11 v ddq v ssq dq2 dq6 v ddq v ss v dd cs# ba0 a3 a5 a7 reset# dq15 v ss dq9 udm dq0 ldqs ldqs# dq4 ras# cas# we# ba2 a0 a2 a9 nc dq12 udqs# udqs dq8 ldm dq1 v dd dq7 ck ck# a10/ap nc a12/bc# a1 a11 nc v ddq dq14 dq10 v ssq v ssq dq3 v ss dq5 v ss v dd zq v refca ba1 a4 a6 a8 v ss v ssq v ddq v dd v ddq v ssq v ssq v ddq nc cke nc v ss v dd v ss v dd v ss notes: 1. ball descriptions listed in table 3 (page 5) are listed as x16. 2. a comma separates the configuration; a slash defines a selectable function. 1gb: x4, x8, x16 ddr3l sdram addendum ball assignments and descriptions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 3: 78-ball fbga C x4, x8 ball descriptions symbol type description a[9:0], a10/ap, a11, a12/bc#, a13 input address inputs: provide the row address for activate commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to deter- mine whether burst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4 burst chop). ba[2:0] input bank address inputs: ba[2:0] define to which bank an activate, read, write, or pre- charge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. out- put data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke enables (registered high) and disables (registered low) internal cir- cuitry and clocks on the dram. the specific circuitry that is enabled/disabled is depend- ent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle) or ac- tive power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buf- fers (excluding cke and reset#) are disabled during self refresh. cke is referenced to v refca . cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for exter- nal rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with the input data during a write access. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v refdq . dm has an optional use as tdqs on the x8 device. odt input on-die termination: odt enables (registered high) and disables (registered low) ter- mination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[7:0], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v ddq . reset# assertion and de-assertion are asynchronous. dq[3:0] i/o data input/output: bidirectional data bus for the x4 configuration. dq[3:0] are refer- enced to v refdq . 1gb: x4, x8, x16 ddr3l sdram addendum ball assignments and descriptions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 3: 78-ball fbga C x4, x8 ball descriptions (continued) symbol type description dq[7:0] i/o data input/output: bidirectional data bus for the x8 configuration. dq[7:0] are refer- enced to v refdq . dqs, dqs# i/o data strobe: output with read data. edge-aligned with read data. input with write da- ta. center-aligned to write data. tdqs, tdqs# i/o termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termination resistance. v dd supply power supply: 1.35v, 1.2825v to 1.45v operational; compatible with 1.5v operation. v ddq supply dq power supply: 1.35v, 1.2825v to 1.45v operational; compatible with 1.5v operation. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (including self re- fresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (rzq), which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). nf C no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. 1gb: x4, x8, x16 ddr3l sdram addendum ball assignments and descriptions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 4: 96-ball fbga C x16 ball descriptions symbol type description a[9:0], a10/ap, a11, a12/bc# input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/write commands, to select one loca- tion out of the memory array in the respective bank. a10 sampled during a pre- charge command determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also pro- vide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burst chop (on-the-fly) will be per- formed (high = bl8 or no burst chop, low = bc4). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are refer- enced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke enables (registered high) and disables (registered low) internal circuitry and clocks on the dram. the specific circuitry that is enabled/disabled is de- pendent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle) or active power-down (row active in any bank). cke is synchronous for power- down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during pow- er-down. input buffers (excluding cke and reset#) are disabled during self re- fresh. cke is referenced to v refca . cs# input chip select: cs# enables (registered low) and disables (registered high) the com- mand decoder. all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . ldm input input data mask: ldm is a lower byte, input mask signal for write data. lower-byte input data is masked when ldm is sampled high along with the input data during a write access. although the ldm ball is input-only, the ldm loading is designed to match that of the dq and dqs balls. ldm is referenced to v refdq . odt input on-die termination: odt enables (registered high) and disables (registered low) termination resistance internal to the ddr3 sdram. when enabled in normal opera- tion, odt is only applied to each of the following balls: dq[15:0], ldqs, ldqs#, udqs, udqs#, ldm, and udm for the x16; dq0[7:0], dqs, dqs#, dm/tdqs, and nf/ tdqs# (when tdqs is enabled) for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command be- ing entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input re- ceiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v ddq . reset# assertion and de-assertion are asynchronous. 1gb: x4, x8, x16 ddr3l sdram addendum ball assignments and descriptions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 4: 96-ball fbga C x16 ball descriptions (continued) symbol type description udm input input data mask: udm is an upper-byte, input mask signal for write data. upper- byte input data is masked when udm is sampled high along with that input data during a write access. although the udm ball is input-only, the udm loading is designed to match that of the dq and dqs balls. udm is referenced to v refdq . dq[7:0] i/o data input/output: lower byte of bidirectional data bus for the x16 configuration. dq[7:0] are referenced to v refdq . dq[15:8] i/o data input/output: upper byte of bidirectional data bus for the x16 configuration. dq[15:8] are referenced to v refdq . ldqs, ldqs# i/o lower byte data strobe: output with read data. edge-aligned with read data. in- put with write data. center-aligned to write data. udqs, udqs# i/o upper byte data strobe: output with read data. edge-aligned with read data. in- put with write data. dqs is center-aligned to write data. v dd supply power supply: 1.35v, 1.2825v to 1.45v. v ddq supply dq power supply: 1.35v, 1.2825v to 1.45v. v refca supply reference voltage for control, command, and address: v refca must be main- tained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (excluding self refresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq reference external reference ball for output drive calibration: this ball is tied to an exter- nal 240 resistor (rzq), which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). 1gb: x4, x8, x16 ddr3l sdram addendum ball assignments and descriptions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
package dimensions figure 3: 78-ball fbga C x4, x8; (jp) ball a1 id 1.2 max 0.8 typ 0.8 0.1 seating plane a 9.6 ctr 6.4 ctr 0.12 a 78x ?0.45 11.5 0.15 ball a1 id 0.8 typ 8 0.15 0.25 min 9 8 7 3 2 1 a b c d e f g h j k l m n dimensions apply to solder balls post- reflow on ?0.33 nsmd ball pads. note: 1. all dimensions are in millimeters. 1gb: x4, x8, x16 ddr3l sdram addendum package dimensions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
figure 4: 96-ball fbga C x16 (jt) ball a1 id 1.2 max 0.8 typ 8 0.15 0.8 0.1 seating plane a 12 ctr 6.4 ctr 0.12 a 96x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 14 0.15 ball a1 id 0.8 typ 0.25 min 9 8 7 3 2 1 a b c d e f g h j k l m n p r t note: 1. all dimensions are in millimeters. 1gb: x4, x8, x16 ddr3l sdram addendum package dimensions pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
electrical characteristics C i dd specifications table 5: i dd maximum limits C rev. f speed bin ddr3l-1066 ddr3l-1333 units i dd width i dd0 x4 65 75 ma x8 85 95 ma i dd1 x4 80 90 ma x8 100 110 ma i dd2po all 8 10 ma i dd2p1 all 25 30 ma i dd2q all 45 55 ma i dd2n all 45 55 ma i dd2nt all 65 75 ma i dd3p all 30 37 ma i dd3n x4, x8 50 60 ma i dd4r x4 120 145 ma x8 120 145 ma i dd4w x4 120 145 ma x8 120 145 ma i dd5b all 175 185 ma i dd6 all 6 6 ma i dd6et all 9 9 ma i dd7 x4 230 300 ma x8 290 360 ma i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma ma 1gb: x4, x8, x16 ddr3l sdram addendum electrical characteristics C i dd specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 6: i dd maximum limits C die rev g speed bin ddr3-1066 ddr3-1333 ddr3-1600 unit i dd width i dd0 x4 65 70 75 ma x8 65 70 75 ma x16 80 85 90 ma i dd1 x4 80 85 90 ma x8 80 85 90 ma x16 110 115 120 ma i dd2p0 (slow) all 12 12 12 ma i dd2p1 (fast) all 25 30 35 ma i dd2q all 40 45 45 ma i dd2n all 40 45 45 ma i dd2nt x4, x8 50 50 55 ma x16 60 65 70 ma i dd3p all 30 35 35 ma i dd3n x4, x8 40 45 45 ma x16 50 50 50 ma i dd4r x4 110 130 145 ma x8 110 130 145 ma x16 150 175 200 ma i dd4w x4 115 135 150 ma x8 115 135 150 ma x16 165 190 215 ma i dd5b all 165 170 175 ma i dd6 all 8 8 8 ma i dd6et all 10 10 10 ma i dd7 x4 200 245 250 ma x8 200 245 250 ma x16 250 275 310 ma i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 1gb: x4, x8, x16 ddr3l sdram addendum electrical characteristics C i dd specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
electrical specifications table 7: input/output capacitance gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet capacitance parame- ters symbol ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 unit s min max min max min max min max single-end i/o: dq, dm c io 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.3 pf differential i/o: dqs, dqs#, tdqs, tdqs# c io 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.3 pf inputs (ctrl, cmd,addr) c i 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.3 pf table 8: dc electrical characteristics and operating conditions C 1.35v operation all voltages are referenced to v ss parameter/condition symbol min nom max units notes supply voltage v dd 1.283 1.35 1.45 v 1, 2, 3, 4 i/o supply voltage v ddq 1.283 1.35 1.45 v 1, 2, 3, 4 notes: 1. maximum dc value may not be greater than 1.425v. the dc value is the linear average of v dd /v ddq (t) over a very long period of time (e.g., 1 sec). 2. if the maximum limit is exceeded, input levels shall be governed by ddr3 specifications. 3. under these supply voltages, the device operates to this ddr3l specification. 4. once initialized for ddr3l operation, ddr3 operation may only be used if the device is in reset while v dd and v ddq are changed for ddr3 operation (see figure 5 (page 21)). table 9: dc electrical characteristics and operating conditions C 1.5v operation all voltages are referenced to v ss parameter/condition symbol min nom max units notes supply voltage v dd 1.425 1.5 1.575 v 1, 2, 3 i/o supply voltage v ddq 1.425 1.5 1.575 v 1, 2, 3 notes: 1. if the minimum limit is exceeded, input levels shall be governed by ddr3l specifications. 2. under 1.5v operation, this ddr3l device operates in accordance with the ddr3 specifica- tions under the same speed timings as defined for this device. 3. once initialized for ddr3 operation, ddr3l operation may only be used if the device is in reset while v dd and v ddq are changed for ddr3l operation (see figure 5 (page 21)). table 10: input switching conditions C command and address parameter/condition symbol ddr3l-800/1066 ddr3l-1333/1600 units input high ac voltage: logic 1 v ih(ac160)min 160 160 mv input high ac voltage: logic 1 v ih(ac135)min 135 135 mv input high dc voltage: logic 1 v ih(dc90)min 90 90 mv input low ac voltage: logic 0 v il(ac160)min C160 C160 mv input low ac voltage: logic 0 v il(ac135)min C135 C135 mv 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 10: input switching conditions C command and address (continued) parameter/condition symbol ddr3l-800/1066 ddr3l-1333/1600 units input low dc voltage: logic 0 v il(dc90)min C90 C90 mv table 11: input switching conditions C dq and dm parameter/condition symbol ddr3l-800/1066 ddr3l-1333/1600 units input high ac voltage: logic 1 v ih(ac160)min 160 C mv input high ac voltage: logic 1 v ih(ac135)min 135 135 mv input high dc voltage: logic 1 v ih(dc90)min 90 90 mv input low ac voltage: logic 0 v il(ac160)min C160 C mv input low ac voltage: logic 0 v il(ac135)min C135 C135 mv input low dc voltage: logic 0 v il(dc90)min C90 C90 mv table 12: differential input operating conditions (ck, ck# and dqs, dqs#) parameter/condition symbol min max units differential input logic high C slew v ih,diff(ac)slew 180 n/a mv differential input logic low C slew v il,diff(ac)slew n/a C180 mv differential input logic high v ih,diff(ac) 2 (v ih(ac) - v ref ) v dd /v ddq mv differential input logic low v il,diff(ac) v ss /v ssq 2 (v ref - v il(ac) ) mv single-ended high level for strobes v seh v ddq /2 + 160 v ddq mv single-ended high level for ck, ck# v dd /2 + 160 v dd mv single-ended low level for strobes v sel v ssq v ddq /2 - 160 mv single-ended low level for ck, ck# v ss v dd /2 - 160 mv table 13: required time t dvac for ck/ck#, dqs/dqs# differential for ac ringback slew rate (v/ns) t dvac at 320mv (ps) t dvac at 270mv (ps) >4.0 70 209 4.0 53 198 3.0 47 194 2.0 35 186 1.8 31 184 1.6 26 181 1.4 20 177 1.2 12 171 1.0 0 164 <1.0 0 164 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 14: r tt effective impedance gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet mr1 [9, 6, 2] r tt resistor v out min nom max units 0, 1, 0 120 r tt,120pd240 0.2 v ddq 0.6 1.0 1.15 r zq /1 0.5 v ddq 0.9 1.0 1.15 r zq /1 0.8 v ddq 0.9 1.0 1.45 r zq /1 r tt,120pu240 0.2 v ddq 0.9 1.0 1.45 r zq /1 0.5 v ddq 0.9 1.0 1.15 r zq /1 0.8 v ddq 0.6 1.0 1.15 r zq /1 120 v il(ac) to v ih(ac) 0.9 1.0 1.65 r zq /2 0, 0, 1 60 r tt,60pd120 0.2 v ddq 0.6 1.0 1.15 r zq /2 0.5 v ddq 0.9 1.0 1.15 r zq /2 0.8 v ddq 0.9 1.0 1.45 r zq /2 r tt,60pu120 0.2 v ddq 0.9 1.0 1.45 r zq /2 0.5 v ddq 0.9 1.0 1.15 r zq /2 0.8 v ddq 0.6 1.0 1.15 r zq /2 60 v il(ac) to v ih(ac) 0.9 1.0 1.65 r zq /4 0, 1, 1 40 r tt,40pd80 0.2 v ddq 0.6 1.0 1.15 r zq /3 0.5 v ddq 0.9 1.0 1.15 r zq /3 0.8 v ddq 0.9 1.0 1.45 r zq /3 r tt,40pu80 0.2 v ddq 0.9 1.0 1.45 r zq /3 0.5 v ddq 0.9 1.0 1.15 r zq /3 0.8 v ddq 0.6 1.0 1.15 r zq /3 40 v il(ac) to v ih(ac) 0.9 1.0 1.65 r zq /6 1, 0, 1 30 r tt,30pd60 0.2 v ddq 0.6 1.0 1.15 r zq /4 0.5 v ddq 0.9 1.0 1.15 r zq /4 0.8 v ddq 0.9 1.0 1.45 r zq /4 r tt,30pu60 0.2 v ddq 0.9 1.0 1.45 r zq /4 0.5 v ddq 0.9 1.0 1.15 r zq /4 0.8 v ddq 0.6 1.0 1.15 r zq /4 30 v il(ac) to v ih(ac) 0.9 1.0 1.65 r zq /8 1, 0, 0 20 r tt,20pd40 0.2 v ddq 0.6 1.0 1.15 r zq /6 0.5 v ddq 0.9 1.0 1.15 r zq /6 0.8 v ddq 0.9 1.0 1.45 r zq /6 r tt,20pu40 0.2 v ddq 0.9 1.0 1.45 r zq /6 0.5 v ddq 0.9 1.0 1.15 r zq /6 0.8 v ddq 0.6 1.0 1.15 r zq /6 20 v il(ac) to v ih(ac) 0.9 1.0 1.65 r zq /12 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 15: reference settings for odt timing measurements gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet measured parameter r tt,nom setting r tt(wr) setting v sw1 v sw2 t aon r zq /4 (60) n/a 50mv 100mv r zq /12 (20) n/a 100mv 200mv t aof r zq /4 (60) n/a 50mv 100mv r zq /12 (20) n/a 100mv 200mv t aonpd r zq /4 (60) n/a 50mv 100mv r zq /12 (20) n/a 100mv 200mv t aofpd r zq /4 (60) n/a 50mv 100mv r zq /12 (20) n/a 100mv 200mv t adc r zq /12 (20) r zq /2 (20) 200mv 250mv table 16: 34 driver impedance characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet mr1 [5, 1] r on resistor v out min nom max 1 units 0, 1 34.3 r on,34pd 0.2 v ddq 0.6 1.0 1.15 r zq /7 0.5 v ddq 0.9 1.0 1.15 r zq /7 0.8 v ddq 0.9 1.0 1.45 r zq /7 r on,34pu 0.2 v ddq 0.9 1.0 1.45 r zq /7 0.5 v ddq 0.9 1.0 1.15 r zq /7 0.8 v ddq 0.6 1.0 1.15 r zq /7 pull-up/pull-down mismatch (mm pupd ) v il(ac) to v ih(ac) C10 n/a 10 % note: 1. a larger maximum limit will result in slightly lower minimum currents. table 17: 40 driver impedance characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet mr1 [5, 1] r on resistor v out min nom max 1 units 0, 0 40 r on,40pd 0.2 v ddq 0.6 1.0 1.15 r zq /6 0.5 v ddq 0.9 1.0 1.15 r zq /6 0.8 v ddq 0.9 1.0 1.45 r zq /6 r on,40pu 0.2 v ddq 0.9 1.0 1.45 r zq /6 0.5 v ddq 0.9 1.0 1.15 r zq /6 0.8 v ddq 0.6 1.0 1.15 r zq /6 pull-up/pull-down mismatch (mm pupd ) v il(ac) to v ih(ac) C10 n/a 10 % note: 1. a larger maximum limit will result in slightly lower minimum currents. 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 18: single-ended output driver characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet parameter/condition symbol min max units output slew rate: single-ended; for rising and falling edges, measure between v ol(ac) = v ref - 0.09 v ddq and v oh(ac) = v ref +0.09 v ddq srq se 1.75 6 v/ns table 19: differential output driver characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet parameter/condition symbol min max units output slew rate: differential; for rising and falling edges, measure between v ol,diff(ac) = C0.18 v ddq and v oh,diff(ac) = +0.18 v ddq srq diff 3.5 12 v/ns output differential crosspoint voltage v ox(ac) v ref - 135 v ref + 135 mv table 20: electrical characteristics and ac operating conditions parameter symbol ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 units min max min max min max min max dq input timing data setup time to dqs, dqs# base (specification) t ds (ac160) 90 C 40 C n/a C n/a C ps v ref @ 1 v/ns 250 C 200 C n/a C n/a C ps data setup time to dqs, dqs# base (specification) t ds (ac135) 140 C 90 C 45 C 25 C ps v ref @ 1 v/ns 275 C 225 C 180 C 160 C ps data hold time from dqs, dqs# base (specification) t dh (dc90) 160 C 110 C 75 C 55 C ps v ref @ 1 v/ns 250 C 200 C 165 C 145 C ps command and address timing ctrl, cmd, addr setup to ck, ck# base (specification) t is (ac160) 215 C 140 C 80 C 60 C ps v ref @ 1 v/ns 375 C 300 C 240 C 220 C ps ctrl, cmd, addr setup to ck, ck# base (specification) t is (ac135) 365 C 290 C 205 C 185 C ps v ref @ 1 v/ns 500 C 425 C 340 C 320 C ps ctrl, cmd, addr hold from ck, ck# base (specification) t ih (dc90) 285 C 210 C 150 C 130 C ps v ref @ 1 v/ns 375 C 300 C 240 C 220 C ps 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 21: derating values for t is/ t ih C ac160/dc90-based t is, t ih derating (ps) C ac/dc-based cmd/addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih 2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 C1 C3 C1 C3 C1 C3 7 5 15 13 23 21 31 31 39 47 0.8 C3 C8 C3 C8 C3 C8 5 1 13 9 21 17 29 27 37 43 0.7 C5 C13 C5 C13 C5 C13 3 C5 11 3 19 11 27 21 35 37 0.6 C8 C20 C8 C20 C8 C20 0 C12 8 C4 16 4 24 14 32 30 0.5 C20 C30 C20 C30 C20 C30 C12 C22 C4 C14 4 C6 12 4 20 20 0.4 C40 C45 C40 C45 C40 C45 C32 C37 C24 C29 C16 C21 C8 C11 0 5 table 22: derating values for t is/ t ih C ac135/dc90-based t is, t ih derating (ps) C ac/dc-based cmd/addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih 2.0 68 45 68 45 45 45 76 53 84 61 92 69 100 79 108 95 1.5 45 30 45 30 30 30 53 38 61 46 69 54 77 64 85 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 C3 2 C3 2 C3 10 5 18 13 26 21 34 31 42 47 0.8 3 C8 3 C8 3 C8 11 1 19 9 27 17 35 27 43 43 0.7 6 C13 6 C13 6 C13 14 C5 22 3 30 11 38 21 46 37 0.6 9 C20 9 C20 9 C20 17 C12 25 C4 33 4 41 14 49 30 0.5 5 C30 5 C30 5 C30 13 C22 21 C14 29 C6 37 4 45 20 0.4 C3 C45 C3 C45 C3 C45 6 C37 14 C29 22 C21 30 C11 38 5 table 23: required time t vac above v ih(ac) (below v il[ac] ) for valid add/cmd transition slew rate (v/ns) t vac at 160mv (ps) t vac at 135mv (ps) >2.0 70 209 2.0 53 198 1.5 47 194 1.0 35 186 0.9 31 184 0.8 26 181 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 23: required time t vac above v ih(ac) (below v il[ac] ) for valid add/cmd transition (contin- ued) slew rate (v/ns) t vac at 160mv (ps) t vac at 135mv (ps) 0.7 20 177 0.6 12 171 0.5 0 164 <0.5 0 164 table 24: derating values for t ds/ t dh C ac160/dc90-based t ds, t dh derating (ps) C ac/dc-based dq slew rate v/ns dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 80 45 80 45 80 45 1.5 53 30 53 30 53 30 61 38 1.0 0 0 0 0 0 0 8 8 16 16 0.9 C1 C3 C1 C3 7 5 15 13 23 21 0.8 C3 C8 5 1 13 9 21 17 29 27 0.7 C3 C5 11 3 19 11 27 21 35 37 0.6 8 C4 16 4 24 14 32 30 0.5 4 6 12 4 20 20 0.4 C8 C11 0 5 table 25: derating values for t ds/ t dh C ac135/dc90-based t ds, t dh derating (ps) C ac/dc-based dq slew rate v/ns dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 68 45 68 45 68 45 1.5 45 30 45 30 45 30 53 38 1.0 0 0 0 0 0 0 8 8 16 16 0.9 2 C3 2 C3 10 5 18 13 26 21 0.8 3 C8 11 1 19 9 27 17 35 27 0.7 14 C5 22 3 30 11 38 21 46 37 0.6 25 C4 33 4 41 14 49 30 0.5 39 C6 37 4 45 20 0.4 30 C11 38 5 1gb: x4, x8, x16 ddr3l sdram addendum electrical specifications pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 26: required time t vac above v ih(ac) (below v il(ac) ) for valid dqtransition slew rate (v/ns) t vac at 160mv (ps) t vac at 135mv (ps) >2.0 70 109 2.0 53 98 1.5 47 94 1.0 35 86 0.9 31 84 0.8 26 81 0.7 20 77 0.6 12 71 0.5 0 64 <0.5 0 64 initialization if the sdram is powered up and initialized for the 1.35v operating voltage range, volt- age can be increased to the 1.5v operating range provided that: ? just prior to increasing the 1.35v operating voltages, no further commands are issued, other than nops or command inhibits, and all banks are in the precharge state. ? the 1.5v operating voltages are stable prior to issuing new commands, other than nops or command inhibits. ? the dll is reset and relocked after the 1.5v operating voltages are stable and prior to any read command. ? the zq calibration is performed. t zqinit must be satisfied after the 1.5v operating vol- tages are stable and prior to any read command. if the sdram is powered up and initialized for the 1.5v operating voltage range, voltage can be reduced to the 1.35v operation range provided that: ? just prior to reducing the 1.5v operating voltages, no further commands are issued, other than nops or command inhibits, and all banks are in the precharge state. ? the 1.35v operating voltages are stable prior to issuing new commands, other than nops or command inhibits. ? the dll is reset and relocked after the 1.35v operating voltages are stable and prior to any read command. ? the zq calibration is performed. t zqinit must be satisfied after the 1.35v operating voltages are stable and prior to any read command. 1gb: x4, x8, x16 ddr3l sdram addendum initialization pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
v dd voltage switching after the ddr3l dram is powered up and initialized, the power supply can be altered between the ddr3l and ddr3 levels, provided the sequence in figure 5 is maintained. figure 5: v dd voltage switching ( ) ( ) ( ) ( ) cke r tt ba ( ) ( ) ( ) ( ) ck, ck# command note 1 note 1 ( ) ( ) ( ) ( ) td tc tg dont care ( ) ( ) ( ) ( ) ( ) ( ) t is odt ( ) ( ) ( ) ( ) th t mrd t mod ( ) ( ) ( ) ( ) mrs mrs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t mrd t mrd ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mrs mr0 mr1 mr3 mrs mr2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ti tj tk ( ) ( ) ( ) ( ) reset# ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t = 500s ( ) ( ) ( ) ( ) ( ) ( ) te ta tb tf ( ) ( ) ( ) ( ) zqcl ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t is static low in case r t t ,nom is enabled at time tg, otherwise static high or low ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t is t is t xpr ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) time break t min = 10ns t min = 10ns t min = 10ns t min = 200s t cksrx v dd , v ddq (ddr3) ( ) ( ) ( ) ( ) t dllk ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t zqinit ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) v dd , v ddq (ddr3l) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) valid valid valid valid ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note: 1. from time point td until tk, nop or des commands must be applied between mrs and zqcl commands. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 1gb: x4, x8, x16 ddr3l sdram addendum initialization pdf: 09005aef833b7221 1gb_1_35v_ddr3l.pdf - rev. f 2/11 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.

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